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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
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PS11017 PS11017
FLAT-BASE TYPE FLAT-BASE TYPE INSULATED TYPE INSULATED TYPE
PS11017
INTEGRATED FUNCTIONS AND FEATURES
* 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technologies. * Circuit for dynamic braking of motor regenerative energy. * Inverter output current capability IO (Note 1): Type Name 100% load 150% over load 17.0A (rms) 25.5A (rms), 1min PS11017 (Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO x 2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
* For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC), Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV). * For N-Side IGBTs : Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), System Over-temperature protection (OT), Fault output (FO) signaling circuit, and Current-Limit warning signal output (CL) * For Brake circuit IGBT : Drive circuit * Warning and Fault signaling : FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV) FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition * For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3). * Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applications.
PACKAGE OUTLINES
4-R2 56 0.8 15.5 4-4.5
MOUNTING HOLE
20.4 1
Terminals Assignment: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CBU+ CBU- CBV+ CBV- CBW+ CBW- GND NC VDH CL FO1 FO2 FO3 CU CV CW UP VP WP UN VN WN Br 31 32 33 34 35 36 P Br N U V W
10
2 0.3
5
0.5
1
7
23
0.5 4-R5
4- 5
6 0.3
(22)
41 0.5
15.5
60 0.5 1 0.3
(102)
15.5
3
31
5
1
36
10
12.7 0.3 63.5 0.8 105 0.5 115 1 96 2.5 17.5
63 0.8
76 1
50
32
5
4-3.2 3 17 0.8
LABEL
(Fig. 1)
May 2001
8.5
13
MITSUBISHI SEMICONDUCTOR
PS11017
FLAT-BASE TYPE INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
Application Specific Intelligent Power Module Protection Circuit Level shifter
Drive Circuit
P
Brake resistor connection, Inrush prevention circuit, etc. AC 200V line input
B
R S T
Z C
CBW+
CBW-
CBU+
CBU-
CBV+
CBV-
U V W
M
AC 200V line output
N
Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit may become necessary depending on the application environment].
T S
Current sensing circuit Input signal conditioning
CU CV CW UP VP WP UN VN WN Br
Drive Circuit
Fo Logic
Protection circuit
Control supply fault sense GND VDH
CL, FO1, FO2, FO3
Analogue signal output corresponding to PWM input each phase current (5V line) Note 1) (5V line) Note 2)
Fault output (5V line) Note 3)
Note 1) To prevent chances of signal oscillation, a series resistor (1k) coupling at each output is recommended. Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolation is possible. Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1k resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to these P and N DC power input pins.
(Fig. 2)
MAXIMUM RATINGS (Tj = 25C) INVERTER PART (Including Brake Part)
Item Supply voltage VCC(surge) Supply voltage (surge) VP or VN VP(S) or VN(S) IC(ICP) IC(ICP) IF(IFP) Symbol VCC Condition Applied between P-N Ratings 450 500 600 600 50 (100) 15 (30) 15 (30) Unit V V V V A A A
Applied between P-N, Surge-value Applied between P-U, V, W, Br or U, V, W, Each output IGBT collector-emitter static voltage Br-N Each output IGBT collector-emitter Applied between P-U, V, W, Br or U, V, W, switching surge voltage Br-N Each output IGBT collector current TC = 25C Brake IGBT collector current Brake diode anode current Note: "( )" means IC peak value
CONTROL PART
Symbol VDH, VDB VCIN VFO IFO VCL ICL ICO Supply voltage Input signal voltage Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current Analogue current signal output current Item Condition Applied between VDH-GND, CBU+-CBU-, CBV+-CBV-, CBW+-CBW- Applied between UP * VP * WP * UN * VN * WN * Br-GND Applied between FO1 * FO2 * FO3-GND Sink current of FO1 * FO2 * FO3 Applied between CL-GND Sink current of CL Sink current of CU * CV * CW Ratings 20 -0.5 ~ 7.5 -0.5 ~ 7 15 -0.5 ~ 7 15 1 Unit V V V mA V mA mA
May 2001
MITSUBISHI SEMICONDUCTOR
PS11017
FLAT-BASE TYPE INSULATED TYPE
TOTAL SYSTEM
Symbol Tj Tstg TC Viso Item Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque Condition (Note 2) -- (Fig. 3) 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M4.0 Ratings -20 ~ +125 -40 ~ +125 -20 ~ +100 2500 0.98 ~ 1.47 Unit C C C Vrms N*m
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. However, these power elements can endure instantaneous junction temperature as high as 150C instantaneously . To make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
LABEL
Tc
(Fig. 3)
THERMAL RESISTANCE
Symbol Rth(j-c)Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F Rth(c-f) Item Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Case to fin, thermal grease applied Condition Min. -- -- -- -- -- Ratings Typ. -- -- -- -- -- Max. 1.75 2.4 2.9 4.5 0.031 Unit C/W C/W C/W C/W C/W
Junction to case Thermal Resistance Contact Thermal Resistance
ELECTRICAL CHARACTERISTICS (Tj = 25C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol VCE(sat) VEC VCE(sat)Br VFBr ton tc(on) toff tc(off) trr Item Collector-emitter saturation voltage FWDi forward voltage Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage Condition VDH = VDB = 15V, Input = ON, Tj = 25C, Ic = 50A Tj = 25C, Ic = -50A, Input = OFF VDH = 15V, Input = ON, Tj = 25C, Ic = 15A Tj = 25C, IF = 15A, Input = OFF 1/2 Bridge inductive, Input = ON VCC = 300V, Ic = 50A, Tj = 125C VDH = 15V, VDB = 15V Note : ton, toff include delay time of the internal control circuit VCC 400V, Input = ON (one-shot) Tj = 125C start 13.5V VDH = VDB 16.5V VCC 400V, Tj 125C, Switching SOA IDH Vth(on) Vth(off) Ri Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resister Integrated between input terminal-VDH Ic < IOL(CL) operation level, Input = ON, 13.5V VDH = VDB 16.5V VDH = 15V, VCIN = 5V Min. -- -- -- -- 0.40 -- -- -- -- Ratings Typ. -- -- -- -- 0.8 0.40 1.5 0.6 0.15 Max. 2.9 2.9 3.5 2.9 2.0 1.0 2.4 1.3 -- Unit V V V V s s s s s
Switching times
FWD reverse recovery time Short circuit endurance (Output, Arm, and Load, Short Circuit Modes)
* No destruction * FO output by protection operation * No destruction * No protecting operation * No FO output -- 0.8 2.5 -- -- 1.4 3.0 150 150 2.0 4.0 -- mA V V k
May 2001
MITSUBISHI SEMICONDUCTOR
PS11017
FLAT-BASE TYPE INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol fPWM txx tdead tint VCO Item PWM input frequency Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Input inter-lock sensing Condition TC 100C, Tj 125C (Note 3) VDH = 15V, TC = -20C ~ +100C Relates to corresponding inputs, (Except brake part), TC = -20C ~ +100C Relates to corresponding input (Except break part) Ic = 0A Ic = IOP(200%) Ic = -IOP(200%) VDH = 15V TC = -20C ~ 100C (Fig. 4) Min. -- 1 2.5 -- 1.87 0.77 2.97 -- -- (Fig. 4) |VCO-VC(200%)| Correspond to max. 500s data hold period (Fig. 5) only, Ic = IOP(200%) After input signal trigger point Open collector output VD = 15V, TC = -20C ~ 100C Tj = 25C VDH = 15V (Note 4) (Fig. 8) 4.0 -- -5 -- -- -- 48.2 79.2 100 -- 11.05 11.55 TC = -20 ~ +100C, Tj 125C 18.00 16.50 10.0 10.5 -- -- -- Ratings Typ. -- -- -- 65 2.27 1.17 3.37 15 -- -- 1.1 -- 3 -- 1 60.0 102 110 90 12.00 12.50 19.20 17.50 11.0 11.5 10 -- 1 Max. 15 500 -- 100 2.57 1.47 3.67 -- 0.7 -- -- 5 -- 1 -- 72.0 -- 120 -- 12.75 13.25 20.15 18.65 12.0 12.5 -- 1 -- Unit kHz s s ns V V V mV V V V % s A mA A A C C V V V V V V s A mA
VC+(200%) Analogue signal linearity with output current VC-(200%) Offset change area vs temperature |VCO| VC+ VC- Analogue signal output voltage limit VC(200%) Analogue signal over all linear variation rCH td(read) ICL(H) ICL(L) IOL SC OT OTr UVDH UVDHr OVDH OVDHr UVDB UVDBr tdV IFO(H) IFO(L) Analogue signal data hold accuracy Analogue signal reading time Signal output current of CL operation Idle Active
VDH = 15V, TC = -20C ~ 100C Ic > IOP(200%), VDH = 15V
CL warning operation level Short circuit over current trip level Trip level Over temperature protection Reset level Trip level Reset level Trip level Supply circuit under & over voltage protection Reset level Trip level Reset level Filter time Fault output current Idle Active
(Fig. 7) (Note 5)
Open collector output
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its FO1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol VCC VDH, VDB Item Supply voltage Control Supply voltage Condition Applied across P-N terminals Applied between VDH-GND, CBU+-CBU-, CBV+-CBV-, CBW+-CBW- Ratings 400 (max.) 151.5 1 (max.) 0 ~ 0.3 4.8 ~ 5.0 Using application circuit Using application circuit 2 ~ 15 2.5 (min.) Unit V V V/s V V kHz s
VDH, VDB Supply voltage ripple Input on voltage VCIN(on) VCIN(off) fPWM tdead Input off voltage PWM Input frequency Arm shoot-through blocking time
May 2001
MITSUBISHI SEMICONDUCTOR
PS11017
FLAT-BASE TYPE INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY
5 VC- 4 min
max VC-(200%) VDH=15V TC=-20~100C
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING "DATA HOLD" DEFINITION
VC
500s
0V
3
VC0
VCH(5s) VCH(505s)-VCH(5s) VCH(5s)
VCH(505s)
VC(V)
2
VC+(200%)
rCH=
1
Analogue output signal data hold range
VC+
0 -400 -300 -200 -100
Note ; Ringing happens around the point where the signal output voltage changes state from "analogue" to "data hold" due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 s delayed point.
0
100 200 300 400
Real load current peak value.(%)(Ic=Io! 2)
(Fig. 4)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm Input signal VCIN(n) of each phase lower arm 0V Gate signal Vo(p) of each phase upper arm (ASIPM internal) Gate signal Vo(n) of each phase upper arm (ASIPM internal) Error output FO1 0V
0V
0V 0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in "LOW" level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and "FO" signal is outputted. After an "input interlock" operation the circuit is latched. The "FO" is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase upper arm Short circuit sensing signal VS
0V 0V
SC delay time
Gate signal Vo of each phase upper arm(ASIPM internal) Error output FO1
0V 0V
Note : Short circuit protection operation. The protection operates with "FO" flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the "Brake").
May 2001
MITSUBISHI SEMICONDUCTOR
PS11017
FLAT-BASE TYPE INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
N-side IGBT Current
off
N-side FWDi Current
VCIN V(hold) IC
on on off
0
+ICL
(VS)
0
-ICL
t(hold) Ref
VC
0 off
VCL
on
Delay time td(read)
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
5V
ASIPM
5.1k R
DC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO1 output signal
VPN 0 VDH 0 VDB VCIN(N)
0 on
PWM starts a)
UP,VP,WP,UN,VN,WN,Br
R
CPU
10k 0.1nF 0.1nF
F01,F02,F03,CL CU,CV,CW
GND(Logic)
b)
VCIN(P) on VCIN(Br) on FOI
on
a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20s number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) FO1 resetting sequence: Apply ON signals to the following input pins : Br Un/Vn/Wn Up/Vp/Wp in that order.
May 2001

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